1. Field of the Invention
The invention relates generally to a computing system input/output (I/O) architecture wherein one or more main processors (MPUs) communicate with one or more I/O sub-processors (IOPs) to achieve high performance I/O throughput. More specifically, the invention relates to a an I/O system of reducing the overhead incurred in initiating an I/O request and in servicing interrupts associated with completed I/O requests.
2. Background of the Invention
It has long been a problem in the computing arts to maintain high performance I/O throughput to or from peripheral devices while reducing the wasteful overhead processing required to perform the I/O operations. In particular, in multi-user/multi-tasking computing environments, it is important that the I/O overhead be kept to a minimum to permit the main processor to service the needs of other users/tasks as one user/task generates I/O processing.
It is common that I/O peripheral devices are attached to a main processor through I/O controller circuits, I/O controller circuits manage the lower level details of operating a peripheral I/O device to relieve the main processor of this burden. For example, a seek operation on a rotating disk drive requires a significant number of lower level operations relating to servo motor controls, actuator controls, and various sense circuits to detect the proper positioning of the read/write head. When a specific requested operation is completed, the I/O controller circuit would perform the required low level operations, then interrupt the main processor to signify completion and await further instructions.
The speed of peripheral I/O devices has increased steadily over time. For example, rotating disk drive mass storage devices now rotate faster than earlier designs and store data more densely on the recording surface (magnetic or optical recording surfaces). The increased speed of peripheral devices tends to increase the frequency of interruption of the main processor for servicing interrupts indicating completion of I/O requests previously initiated by the main processor. To reduce the number of such interrupts of the main processor, I/O peripheral controller circuits have been designed with increased "intelligence" to reduce the number of interrupts of the main processor associated with completion of each 110 request.
Controller circuits which control I/O peripheral devices attached to a small computer system interface bus (referred to herein as SCSI) exemplify the evolution of "intelligence" in I/O peripheral device controllers. Early (so called "first generation") SCSI I/O peripheral device controller circuits required many low level commands to accomplish a single I/O operation. These early I/O peripheral device controller circuits typically interrupted the main processor following completion of each low level command. In SCSI bus control as performed by first generation SCSI control circuits, a single I/O request may include commands to arbitrate for the SCSI bus, commands to select the target device, commands to request the data transfer, commands to disconnect and reconnect the peripheral from the SCSI bus, and various commands to change the SCSI bus state in association with these other commands. Therefore, a single I/O request could require several low level I/O commands be generated to the I/O controller and would generate a corresponding plurality of interrupt requests to the main processor to indicate completion of the plurality of commands. In this first generation I/O architecture, the main processor and the I/O controller would operate synchronously, each waiting for the other to proceed to its next step. Second generation SCSI controller circuits introduced several multiphase commands which automatically sequenced through several of the states and low level operations required to complete a single I/O request. Fewer commands and corresponding interrupts (possibly as low as one) would be generated to the main processor for each I/O request processed. Many of these second generation I/O controller were capable of handling multiple I/O requests. Third generation SCSI controller circuits added various "scripting" functions to permit more complex command sequences, including some exception conditions, to be handled by the SCSI controller without the need for interrupting the main processor. These third generation devices were capable of continuing processing after generating an interrupt to the main processor. Most such designs could therefore handle multiple I/O requests at the same time.
Other types of I/O peripheral device controller circuits have evolved in ways similar to the SCSI controller circuits. More intelligence has been added to the controller circuits to reduce the number of interrupts of the main processor to nearly one for each I/O request initiated by the main processor. As a further example, network controller circuits (i.e. Ethernet or Token Ring LAN controller circuits) have similar "intelligence" in their designs to reduce the number of interrupts of the main processor. A single I/O request of such intelligent LAN controllers may generate a single interrupt request of the main processor despite the fact that several interim steps or lower level commands may be completed to satisfy the single I/O request.
These prior design improvements in peripheral device controller circuits have helped reduce the overhead processing requirements in the main processor. However, as processor power increases, so increases the demands for processing power within the application programs running on the main processor. Despite these improvements, it remains a problem to reduce the processing overhead required of the main processor to thereby improve the performance of the overall system.
In view of the above it is clear that a need exists for an I/O system architecture which further reduces the I/O overhead processing required of the main processor associated with completion of I/O requests.